1. Technical Field
This invention generally relates to semi-conductor processing. In particular, this invention relates to a die-to-die interconnection structure and a method for fabricating the structure for a stacked and laminated, three dimensional, semi-conductor device, commonly known as CUBE, so that wiring may be constructed on the face of the CUBE.
2. Background Art
The development of CUBE technology has created a need to completely insulate the access, or end plane edges, of the chips without covering the wire leads, which must be in electrical contact with the cube face wiring. Various methods for insulating the cube face or access plane completely, except for the ends of the leads, are available including: (a) photolithographic methods of selectively etching holes or vias through a deposited insulating coating over the wire leads; and (b) photolithographic methods of selectively etching the access plane end of the stacked chips, depositing the insulative layer, and lapping in order to uncover the tips of the leads without removing the insulative layer from the edges of the silicon chips.
U.S. Pat. No. 4,525,921, entitled "High-Density Electronic Processing Package--Structure and Fabrication", by Carson et al., issued Jul. 2, 1985, and assigned to Irvine Sensors Corporation, relates to a stack of semi-conductor chips having circuitry on each chip and the method of fabricating the stacks, including the process for insulating the cube face, except for the ends of the leads. The method includes etching the silicon chips at the cube face, covering the cube face with insulative material, and then lapping to expose the ends of the wire leads. The etch of the cube face of the silicon chips and silicon oxide between the chips is accomplished by a plasma, or charged gas, reacting with photoresist-free substrate (i.e. the silicon chip and insulative material).
U.S. Pat. No. 5,107,586, entitled "Method for Interconnecting a Stack of Integrated Circuits at a Very High Density", by Eichelberger et al., issued Apr. 28, 1992, and assigned to General Electric Company, relates to a method for interconnecting stacks of chips by applying insulator film to the cube faces of the stack of chips and then photolithographically creating vias through the insulative layer, forming an interconnect pattern on top of the insulative layer and then electroplating the interconnect pattern.
As described in the above-cited patents, via etching by photo-lithographic means and silicon chip etching have been used as methods to allow the lead wires running along the chip's faces to be interconnected at the cube face while allowing insulation of the cube faces. See U.S. Pat. No. 4,238,755 (a multi-layered integrated circuit wherein the chips plug into a detector chip, the only insulative material between the chips and the detector chip is the atmosphere surrounding the chip); U.S. Pat. No. 4,627,737 (photo-detector array module having a stack of semi-conductor chips formed by the etch, insulate, lap method); U.S. Pat. No. 4,770,640 (electrical interconnection device for integrated circuits produced by a photolithographic method of selectively etching vias through the insulative coating); U.S. Pat. No. 5,016,138 (high density package for integrated circuits in which the chips are placed onto substrate layers of insulative material and then stacked); U.S. Pat. No. 5,051,865 (in a laminated stacked chip structure, the preparation for surface wire connection to the chip surface conductors by polishing back the surface of the structure); and U.S. Pat. No. 5,279,991 (method for fabricating stacks of integrated circuit chips by segmenting larger stacks accomplished by using a thermoplastic adhesive on the plane between the short stacks, no method specifically for insulating the cube face, except for the wire leads, is given). All of the references disclosed herein are hereby incorporated by reference.
The above references do not adequately address the problems involved with photolithographically defining and etching a via through the insulating coating, with the attendant increases in process time, unit hours, tooling, and CUBE build costs. Additionally, the present photolithographic processes may have metallization coverage problems over possibly discontinuous lead-tip/polyimide structures. Therefore, there existed a need to provide electrical contacts on the face of a CUBE without photolithographically defining and etching a via through the insulating coating or etching the access plane edge of the stacked chip, thereby degrading the chip itself.